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VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
14 years 4 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 4 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
VLSID
2008
IEEE
149views VLSI» more  VLSID 2008»
14 years 4 months ago
NBTI Degradation: A Problem or a Scare?
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootka...
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 4 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 4 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
VLSID
2008
IEEE
151views VLSI» more  VLSID 2008»
14 years 4 months ago
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restri...
Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Ros...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 4 months ago
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chos...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
VLSID
2008
IEEE
166views VLSI» more  VLSID 2008»
14 years 4 months ago
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
Shashidhar Mysore, Banit Agrawal, Frederic T. Chon...
VLSID
2008
IEEE
225views VLSI» more  VLSID 2008»
14 years 4 months ago
Formal Verification of a Public-Domain DDR2 Controller Design
This paper demonstrates a formal verificationplanning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC o...
Abhishek Datta, Vigyan Singhal
VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
14 years 4 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal