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DAC
2012
ACM
7 years 9 months ago
STM concurrency control for embedded real-time software with tighter time bounds
We consider software transactional memory (STM) concurrency control for multicore real-time software, and present a novel contention manager (CM) for resolving transactional con...
Mohammed El-Shambakey, Binoy Ravindran
DAC
2012
ACM
7 years 9 months ago
Process variation in near-threshold wide SIMD architectures
Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and par...
Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongj...
DAC
2012
ACM
7 years 9 months ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Moongon Jung, David Z. Pan, Sung Kyu Lim
DAC
2012
ACM
7 years 9 months ago
GDRouter: interleaved global routing and detailed routing for ultimate routability
Improving detailed routing routability is an important objective of a global router. In this paper, we propose GDRouter, an interleaved global routing and detailed routing algorit...
Yanheng Zhang, Chris Chu
DAC
2012
ACM
7 years 9 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...

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jaewleeProfessor, Assistant
Sungkyunkwan University
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DAC
2011
ACM
8 years 6 months ago
Enabling system-level modeling of variation-induced faults in networks-on-chips
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiu...
DAC
2011
ACM
8 years 6 months ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
DAC
2011
ACM
8 years 6 months ago
Enforcing architectural contracts in high-level synthesis
We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation and the user, and (...
Nikhil A. Patil, Ankit Bansal, Derek Chiou
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