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FPGA
2006
ACM
93views FPGA» more  FPGA 2006»
13 years 8 months ago
Measuring the gap between FPGAs and ASICs
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
Ian Kuon, Jonathan Rose
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
13 years 8 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
13 years 8 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
FPGA
2006
ACM
92views FPGA» more  FPGA 2006»
13 years 8 months ago
Embedded floating-point units in FPGAs
Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited t...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
13 years 8 months ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
13 years 8 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
13 years 8 months ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
FPGA
2004
ACM
101views FPGA» more  FPGA 2004»
13 years 8 months ago
SPFD-based one-to-many rewiring
Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambay...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
13 years 8 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
FPGA
2004
ACM
140views FPGA» more  FPGA 2004»
13 years 8 months ago
Using reconfigurability to achieve real-time profiling for hardware/software codesign
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...
Lesley Shannon, Paul Chow