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FS
2011
165views more  FS 2011»
7 years 8 months ago
Asset price bubbles from heterogeneous beliefs about mean reversion rates
Harrison and Kreps showed in 1978 how the heterogeneity of investor beliefs can drive speculation, leading the price of an asset to exceed its intrinsic value. By focusing on an e...
Xi Chen, Robert V. Kohn
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
7 years 8 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
FPGA
2011
ACM
321views FPGA» more  FPGA 2011»
7 years 8 months ago
An analytical model relating FPGA architecture parameters to routability
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
Joydip Das, Steven J. E. Wilton
FPGA
2011
ACM
330views FPGA» more  FPGA 2011»
7 years 8 months ago
CoRAM: an in-fabric memory architecture for FPGA-based computing
FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despit...
Eric S. Chung, James C. Hoe, Ken Mai
FPGA
2011
ACM
393views FPGA» more  FPGA 2011»
7 years 8 months ago
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
Henry Wong, Vaughn Betz, Jonathan Rose
ASPDAC
2011
ACM
215views Hardware» more  ASPDAC 2011»
7 years 8 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...

Publication
266views
7 years 10 months ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...

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tyusemanEngineer
MIPT
tyuseman
But it ain’t about how hard you hit... it’s about how hard you can get hit, and keep moving forward. It’s how much you can take, and keep moving forward. That’s how winning...
TVLSI
2010
7 years 11 months ago
Improving FPGA Performance for Carry-Save Arithmetic
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk,...
JSA
2010
158views more  JSA 2010»
7 years 11 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
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