Sciweavers

FMCAD
2009
Springer
13 years 11 months ago
Finding heap-bounds for hardware synthesis
Abstract—Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during a...
Byron Cook, Ashutosh Gupta, Stephen Magill, Andrey...
FMCAD
2009
Springer
13 years 11 months ago
MCC: A runtime verification tool for MCAPI user applications
Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer,...
FMCAD
2009
Springer
13 years 11 months ago
Software model checking via large-block encoding
Abstract—Several successful approaches to software verificabased on the construction and analysis of an abstract reachability tree (ART). The ART represents unwindings of the co...
Dirk Beyer, Alessandro Cimatti, Alberto Griggio, M...
FMCAD
2009
Springer
13 years 11 months ago
Formal verification of correctness and performance of random priority-based arbiters
Krishnan Kailas, Viresh Paruthi, Brian Monwai
FMCAD
2009
Springer
13 years 11 months ago
Debugging formal specifications using simple counterstrategies
Robert Könighofer, Georg Hofferek, Roderick B...
FMCAD
2009
Springer
13 years 11 months ago
SAT-based synthesis of clock gating functions using 3-valued abstraction
Valued Abstraction Oleg Rokhlenko Joint work with Eli Arbel and Karen Yorav IBM Haifa Research Labs
Eli Arbel, Oleg Rokhlenko, Karen Yorav
FMCAD
2009
Springer
13 years 11 months ago
Connecting pre-silicon and post-silicon verification
Sandip Ray, Warren A. Hunt Jr.
FMCAD
2009
Springer
13 years 11 months ago
Synthesizing robust systems
—Many specifications include assumptions on the environment. If the environment satisfies the assumptions then a correct system reacts as intended. However, when the environmen...
Roderick Bloem, Karin Greimel, Thomas A. Henzinger...
FMCAD
2009
Springer
13 years 11 months ago
Formal verification of analog designs using MetiTarski
William Denman, Behzad Akbarpour, Sofiène T...
FMCAD
2009
Springer
13 years 11 months ago
Scalable conditional equivalence checking: An automated invariant-generation based approach
—Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades...
Jason Baumgartner, Hari Mony, Michael L. Case, Jun...