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ASPDAC
2015
ACM
23views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data
Passive macromodeling for RF circuit blocks is a critical task to facilitate efficient system-level simulation for large-scale RF systems (e.g., wireless transceivers). In this pa...
Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li 000...
ASPDAC
2015
ACM
16views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Electromigration-aware redundant via insertion
As the feature size shrinks, electromigration (EM) becomes a more critical reliability issue in IC design. EM around the via structures accounts for much of the reliability proble...
Jiwoo Pak, Bei Yu, David Z. Pan
ASPDAC
2015
ACM
20views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Early stage real-time SoC power estimation using RTL instrumentation
Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but realtime, long time interval and accurate estimation is still c...
Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-F...
ASPDAC
2015
ACM
17views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power
—Recently, an emerging non-volatile memory called Racetrack Memory (RM) becomes promising to satisfy the requirement of increasing on-chip memory capacity. RM can achieve ultra-h...
Chao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai ...
ASPDAC
2015
ACM
26views Hardware» more  ASPDAC 2015»
5 years 7 months ago
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection
– This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO)....
Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura...
ASPDAC
2015
ACM
26views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis
Abstract—The emerging nonvolatile memory (NVM) technology can potentially change the landscape of future IC designs with numerous benefits, such as high performance, low leakage...
Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie 0001,...
ASPDAC
2015
ACM
19views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Approximation-aware scheduling on heterogeneous multi-core architectures
The high performance demand of embedded systems along with restrictive thermal design power (TDP) constraint have lead to the emergence of the heterogenous multi-core architecture...
Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika...
ASPDAC
2015
ACM
20views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic prices
—Dynamic energy pricing is a promising technique in the Smart Grid to alleviate the mismatch between electricity generation and consumption. Energy consumers are incentivized to ...
Ji Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, Mass...
ASPDAC
2015
ACM
15views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software
—System-Level Design Languages (SLDL) allow component-oriented specifications, e.g. for separating computation and communication. This separation allows for a flexible model co...
Jiaxing Zhang, Sanyuan Tang, Gunar Schirner
ASPDAC
2015
ACM
16views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Toward large-scale access-transistor-free memristive crossbars
Abstract— Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell access-transistor may no longer be necessar...
Amirali Ghofrani, Miguel Angel Lastras-Monta&ntild...
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