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    EURODAC
    1995
    IEEE
    156views VHDL» more  EURODAC 1995»
    KANDIS - a tool for construction of mixed analog/digital systems
    13 years 8 months ago
    KANDIS - a tool for construction of mixed analog/digital systems
    Download  www.ti.cs.uni-frankfurt.de
    The synthesis of electronic circuits on system level o ers the possibility to nd better locations of the A/D interfaces and to determine parameters like clock rates and bit widths...
    Peter Oehler, Christoph Grimm, Klaus Waldschmidt
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    EURODAC
    1995
    IEEE
    155views VHDL» more  EURODAC 1995»
    Design and use of a system-level specification and verification methodology
    13 years 8 months ago
    Design and use of a system-level specification and verification methodology
    Download  www.cs.york.ac.uk
    M. M. Kamal Hashmi, Alistair C. Bruce
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    EURODAC
    1995
    IEEE
    151views VHDL» more  EURODAC 1995»
    Model of conceptual design of complex electronic systems
    13 years 8 months ago
    Model of conceptual design of complex electronic systems
    Download  www.cs.york.ac.uk
    Due to the ever increasing complexity of electronic system (ES) design, the conceptual design phase and its realization in later phases of the design stream have become increasing...
    Alexander N. Soloviev, Alexander L. Stempkovsky
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    EURODAC
    1995
    IEEE
    135views VHDL» more  EURODAC 1995»
    A high performance VHDL simulator for large systems design
    13 years 8 months ago
    A high performance VHDL simulator for large systems design
    Download  www.cs.york.ac.uk
    The requirements of large system design place great demands upon the performance and diagnostic capabilities of simulation. This paper explains how these requirements have been sa...
    Steve Hodgson, Zak Shaar, Andy Smith
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    EURODAC
    1995
    IEEE
    101views VHDL» more  EURODAC 1995»
    Exploiting power-up delay for sequential optimization
    13 years 8 months ago
    Exploiting power-up delay for sequential optimization
    Download  www.cecs.uci.edu
    Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
    Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
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    EURODAC
    1995
    IEEE
    130views VHDL» more  EURODAC 1995»
    Semi-dynamic scheduling of synchronization-mechanisms
    13 years 8 months ago
    Semi-dynamic scheduling of synchronization-mechanisms
    Download  www.cecs.uci.edu
    This paper presents a novel approach to scheduling of hardware supported synchronization operations. The optimization goal is to minimize the interation time of processes and thus...
    Wolfgang Ecker
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    EURODAC
    1995
    IEEE
    294views VHDL» more  EURODAC 1995»
    A classification of design steps and their verification
    13 years 8 months ago
    A classification of design steps and their verification
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    Wolfgang Ecker
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    EURODAC
    1995
    IEEE
    180views VHDL» more  EURODAC 1995»
    Integration of VHDL into a system design environment
    13 years 8 months ago
    Integration of VHDL into a system design environment
    Download  www.cs.york.ac.uk
    Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
    Ludwig Schwoerer, Matthias Lück, Hartmut Schr...
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    EURODAC
    1995
    IEEE
    123views VHDL» more  EURODAC 1995»
    An approach for classification of integrated circuits by a knowledge conserving library concept
    13 years 8 months ago
    An approach for classification of integrated circuits by a knowledge conserving library concept
    Download  www.cecs.uci.edu
    D. Wagenblasst, Wolfgang Thronicke
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    EURODAC
    1995
    IEEE
    131views VHDL» more  EURODAC 1995»
    System level design, a VHDL based approach
    13 years 8 months ago
    System level design, a VHDL based approach
    Download  www.cecs.uci.edu
    A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
    Joris van den Hurk, Edwin Dilling
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