EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
Modern CAD systems allow the designers to come up with powerful programmable datapaths in avery short time. The time to develop compilers for this datapaths is much longer. This p...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
The VOVHDL language was defined as a verification oriented VHDL
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of ...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
This paper introduces a new Generalized Signal Transition Graph model for specifying complex mixed asynchronous/synchronouscircuits, as found in system-level interfaces. Our goal h...