Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
12 years 1 months ago
Post routing performance optimization via tapered link insertion and wiresizing
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
Tianxiong Xue, Ernest S. Kuh
EURODAC
1995
IEEE
146views VHDL» more  EURODAC 1995»
12 years 1 months ago
Practical inter-operation of CAD tools using a flexible procedural interface
This paper addresses the problem of semantic heterogeneity between data representations with particular emphasis on CAD tool data representations. The combination of powerful mapp...
Zahir Moosa, Nick Filer, Michael Brown, J. Heaton,...
EURODAC
1995
IEEE
107views VHDL» more  EURODAC 1995»
12 years 1 months ago
A backplane approach for cosimulation in high-level system specification environments
S. Schmerler, Y. Tanurhan, Klaus D. Müller-Gl...
EURODAC
1995
IEEE
149views VHDL» more  EURODAC 1995»
12 years 1 months ago
Cosimulation of real-time control systems
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...
Juha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrj...
EURODAC
1995
IEEE
150views VHDL» more  EURODAC 1995»
12 years 1 months ago
A reuse scenario for the VHDL-based hardware design flow
Viktor Preis, Renate Henftling, Markus Schütz...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
12 years 1 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
EURODAC
1995
IEEE
134views VHDL» more  EURODAC 1995»
12 years 1 months ago
Area efficient DSP datapath synthesis
Andrew A. Duncan, David C. Hendry
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
12 years 1 months ago
Creating hierarchy in HDL-based high density FGPA design
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
Carol A. Fields
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
12 years 1 months ago
Scalable performance scheduling for hardware-software cosynthesis
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
Thomas Benner, Rolf Ernst, Achim Österling
EURODAC
1995
IEEE
136views VHDL» more  EURODAC 1995»
12 years 1 months ago
Computing subsets of equivalence classes for large FSMs
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...
Gianpiero Cabodi, Stefano Quer, Paolo Camurati
books