EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper addresses the problem of semantic heterogeneity between data representations with particular emphasis on CAD tool data representations. The combination of powerful mapp...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (HDLs) is rapidly supplanting schematic entry ...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...