Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
EURODAC
1995
IEEE
116views VHDL» more  EURODAC 1995»
12 years 1 months ago
An improved relaxation approach for mixed system analysis with several simulation tools
: This paper introduces a modified relaxation approach that allows to improve the convergence of iterations while analyzing mixed systems with different simulators. The method redu...
Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
12 years 1 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
12 years 1 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
12 years 1 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
EURODAC
1995
IEEE
142views VHDL» more  EURODAC 1995»
12 years 1 months ago
Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
E. Leroux, Flavio G. Canavero, G. Vecchi
EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
12 years 1 months ago
On implementation choices for iterative improvement partitioning algorithms
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
12 years 1 months ago
Use of embedded scheduling to compile VHDL for effective parallel simulation
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
John Willis, Zhiyuan Li, Tsang-Puu Lin
EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
12 years 1 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
books