EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
: This paper introduces a modified relaxation approach that allows to improve the convergence of iterations while analyzing mixed systems with different simulators. The method redu...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
EURODAC
1995
IEEE
13 years 7 months ago
1995
IEEE
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...