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EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
12 years 1 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
EURODAC
1995
IEEE
202views VHDL» more  EURODAC 1995»
12 years 1 months ago
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
Santhanam Srinivasan, Niraj K. Jha
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
12 years 1 months ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
EURODAC
1995
IEEE
173views VHDL» more  EURODAC 1995»
12 years 1 months ago
Cooperative concurrency control for design environments
In this paper, we present a new model for concurrency control that supports cooperation of design tools and designers in a design environment. We capture characteristic access and...
Ansgar Bredenfeld
EURODAC
1995
IEEE
153views VHDL» more  EURODAC 1995»
12 years 1 months ago
VHDL-based communication and synchronization synthesis
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
Wolfgang Ecker, Manfred Huber
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
12 years 1 months ago
Towards verifying VHDL descriptions of processors
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
Laurent Arditi, Hélène Collavizza
EURODAC
1995
IEEE
100views VHDL» more  EURODAC 1995»
12 years 1 months ago
A unified approach to the extraction of realistic multiple bridging and break faults
The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets...
Gerald Spiegel, Albrecht P. Stroele
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
12 years 1 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
12 years 1 months ago
Timing constraint specification and synthesis in behavioral VHDL
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
12 years 1 months ago
VHDL quality: synthesizability, complexity and efficiency evaluation
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
M. Mastretti
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