Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
12 years 1 months ago
The VHDL based design of the MIDA MPEG1 audio decoder
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
Andrea Finotello, Maurizio Paolini
EURODAC
1995
IEEE
128views VHDL» more  EURODAC 1995»
12 years 1 months ago
Closeness metrics for system-level functional partitioning
An important system design task is the partitioning of system functionality for implementation among multiple system components, including partitions among hardware and software c...
Frank Vahid, Daniel D. Gajski
EURODAC
1990
IEEE
73views VHDL» more  EURODAC 1990»
12 years 1 months ago
A new method for the state reduction of incompletely specified finite sequential machines
Maria J. Avedillo, José M. Quintana, Jos&ea...
EURODAC
1990
IEEE
72views VHDL» more  EURODAC 1990»
12 years 1 months ago
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler
J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man
EURODAC
1990
IEEE
92views VHDL» more  EURODAC 1990»
12 years 1 months ago
Accelerated test pattern generation by cone-oriented circuit partitioning
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
Torsten Grüning, Udo Mahlstedt, Wilfried Daeh...
EURODAC
1990
IEEE
74views VHDL» more  EURODAC 1990»
12 years 1 months ago
Matching system and component behaviour in MIMOLA synthesis tools
This paper discusses the selection of available components during high-level synthesis. We stress the importance of describing the behaviour of available components in some langua...
Peter Marwedel
EURODAC
1990
IEEE
102views VHDL» more  EURODAC 1990»
12 years 1 months ago
Tools and devices supporting the pseudo-exhaustive test
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
Sybille Hellebrand, Hans-Joachim Wunderlich
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
12 years 1 months ago
A method for partitioning UNITY language in hardware and software
In this paper we introduce a method to partition UNITY system speci cations into software and hardware parts. This method considers di erent design possibilities and de nes cost f...
Xun Xiong, Edna Barros, Wolfgang Rosenstiel
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
12 years 1 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
books