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EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
12 years 1 months ago
A new knowledge-based design manager assistant for CAD frameworks
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
Félix Moreno, Juan M. Meneses
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
12 years 1 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
12 years 1 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
12 years 1 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
EURODAC
1994
IEEE
123views VHDL» more  EURODAC 1994»
12 years 1 months ago
Testing redundant asynchronous circuits by variable phase splitting
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
Luciano Lavagno, Antonio Lioy, Michael Kishinevsky
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
12 years 1 months ago
Design automation of self checking circuits
In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint ...
Sayed Mohammad Kia, Sri Parameswaran
EURODAC
1994
IEEE
115views VHDL» more  EURODAC 1994»
12 years 1 months ago
A tightly coupled approach to design and data management
Flávio Rech Wagner, Lia Goldstein Golendzin...
EURODAC
1994
IEEE
113views VHDL» more  EURODAC 1994»
12 years 1 months ago
Formal verification of pipeline conflicts in RISC processors
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...
Ramayya Kumar, Sofiène Tahar
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
12 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
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