EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
A
exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint ...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...