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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
12 years 1 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
EURODAC
1994
IEEE
163views VHDL» more  EURODAC 1994»
12 years 1 months ago
VHDL and cyclic corrector codes
Cyclic corrector codes, or "block codes", are often used in telecommunications systems. To facilitate the design of coding/decoding circuits using this type of code, we ...
France Mendez
EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
12 years 1 months ago
The semantics of behavioral VHDL '93 descriptions
We present a rigorous but transparent semantic de nition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assi...
Wolfgang Müller 0003, Egon Börger, Uwe G...
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
12 years 1 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
12 years 1 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
EURODAC
1994
IEEE
140views VHDL» more  EURODAC 1994»
12 years 1 months ago
GSA: scheduling and allocation using genetic algorithm
This paper describes a unique approach to scheduling and allocation problem in high-level synthesis using genetic algorithm (GA). This approach is dierent from a previous attempt ...
Ali Shahid, Muhammad S. T. Benten, Sadiq M. Sait
EURODAC
1994
IEEE
124views VHDL» more  EURODAC 1994»
12 years 1 months ago
Automotive databus simulation using VHDL
developed and standardised, for example CAN[1][2], J1850[3]. THE ELECTRONIC VEHICLE TODAYVHDL has been used to develop a simulator for automotive databus networks. This is a design...
Karen Hale
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
12 years 1 months ago
Generating VHDL models from natural language descriptions
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling st...
Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik...
EURODAC
1994
IEEE
377views VHDL» more  EURODAC 1994»
12 years 1 months ago
VHDL switch level fault simulation
Christopher A. Ryan, Joseph G. Tront
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
12 years 1 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...
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