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VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
8 years 1 months ago
A Reconfigurable Architecture for Secure Multimedia Delivery
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
Amit Pande, Joseph Zambreno
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
8 years 1 months ago
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
Koushik Chakraborty, Sanghamitra Roy
VLSID
2010
IEEE
168views VLSI» more  VLSID 2010»
8 years 1 months ago
Robust System Design
Subhasish Mitra
VLSID
2010
IEEE
200views VLSI» more  VLSID 2010»
8 years 1 months ago
Pinpointing Cache Timing Attacks on AES
The paper analyzes cache based timing attacks on optimized codes for Advanced Encryption Standard (AES). The work justifies that timing based cache attacks create hits in the fi...
Chester Rebeiro, Mainack Mondal, Debdeep Mukhopadh...
VLSID
2010
IEEE
202views VLSI» more  VLSID 2010»
8 years 1 months ago
Processor Architecture Design Using 3D Integration Technology
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
Yuan Xie
EAAI
2006
189views more  EAAI 2006»
8 years 3 months ago
Evolutionary algorithms for VLSI multi-objective netlist partitioning
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Aba...
GLVLSI
2008
IEEE
169views VLSI» more  GLVLSI 2008»
8 years 3 months ago
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
8 years 3 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
8 years 3 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
FCCM
2008
IEEE
176views VLSI» more  FCCM 2008»
8 years 3 months ago
The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overhead...
Shannon Koh, Oliver Diessel
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