Sciweavers

DFT
2006
IEEE
148views VLSI» more  DFT 2006»
13 years 5 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
GLVLSI
2010
IEEE
149views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Lightweight runtime control flow analysis for adaptive loop caching
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
Marisha Rawlins, Ann Gordon-Ross
GLVLSI
2010
IEEE
220views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Thermal-aware voltage droop compensation for multi-core architectures
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
Jia Zhao, Basab Datta, Wayne P. Burleson, Russell ...
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
13 years 5 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
GLVLSI
2010
IEEE
183views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors
This paper describes a physics-based semi-analytical model for Schottky-barrier carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model includes the treatment o...
Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, ...
GLVLSI
2010
IEEE
150views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM...
Anuj Pushkarna, Hamid Mahmoodi
GLVLSI
2009
IEEE
201views VLSI» more  GLVLSI 2009»
13 years 6 months ago
Glitch-free design for multi-threshold CMOS NCL circuits
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...
Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia D...
GLVLSI
2009
IEEE
174views VLSI» more  GLVLSI 2009»
13 years 6 months ago
Terahertz sensing technology
Michael S. Shur
DFT
2009
IEEE
210views VLSI» more  DFT 2009»
13 years 6 months ago
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple o...
Nastaran Nemati, Amirhossein Simjour, Amirali Ghof...