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DFT
2009
IEEE
139views VLSI» more  DFT 2009»
8 years 6 months ago
Reduced Precision Checking for a Floating Point Adder
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
VLSID
1994
IEEE
108views VLSI» more  VLSID 1994»
8 years 6 months ago
A New Genetic Algorithm for the Channel Routing Problem
Jens Lienig, Krishnaiyan Thulasiraman
VLSID
1995
IEEE
107views VLSI» more  VLSID 1995»
8 years 6 months ago
Functional test generation for non-scan sequential circuits
Mandyam-Komar Srinivas, James Jacob, Vishwani D. A...
VLSID
1995
IEEE
113views VLSI» more  VLSID 1995»
8 years 6 months ago
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
Luca Penzo, Donatella Sciuto, Cristina Silvano
VLSID
1995
IEEE
97views VLSI» more  VLSID 1995»
8 years 6 months ago
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
VLSID
1995
IEEE
112views VLSI» more  VLSID 1995»
8 years 6 months ago
An efficient automatic test generation system for path delay faults in combinational circuits
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
VLSID
1995
IEEE
104views VLSI» more  VLSID 1995»
8 years 6 months ago
A VLSI architecture for the computation of NURBS patches
Meenakshisundaram Gopi, Swami Manohar
VLSID
1995
IEEE
109views VLSI» more  VLSID 1995»
8 years 6 months ago
Logic minimization based approach for compressing image data
Jacob Augustine, Wen Feng, James Jacob
GLVLSI
1995
IEEE
120views VLSI» more  GLVLSI 1995»
8 years 6 months ago
Performance driven standard-cell placement using the genetic algorithm
Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muham...
GLVLSI
1995
IEEE
118views VLSI» more  GLVLSI 1995»
8 years 6 months ago
A new look at the conditions for the synthesis of speed-independent circuits
Enric Pastor, Jordi Cortadella, Oriol Roig
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