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    DFT
    2009
    IEEE
    139views VLSI» more  DFT 2009»
    Reduced Precision Checking for a Floating Point Adder
    13 years 7 months ago
    Reduced Precision Checking for a Floating Point Adder
    Download  people.ee.duke.edu
    We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
    Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
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    VLSID
    1994
    IEEE
    108views VLSI» more  VLSID 1994»
    A New Genetic Algorithm for the Channel Routing Problem
    13 years 8 months ago
    A New Genetic Algorithm for the Channel Routing Problem
    Download  www.cs.ou.edu
    Jens Lienig, Krishnaiyan Thulasiraman
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    VLSID
    1995
    IEEE
    107views VLSI» more  VLSID 1995»
    Functional test generation for non-scan sequential circuits
    13 years 8 months ago
    Functional test generation for non-scan sequential circuits
    Download  eprints.iisc.ernet.in
    Mandyam-Komar Srinivas, James Jacob, Vishwani D. A...
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    VLSID
    1995
    IEEE
    113views VLSI» more  VLSID 1995»
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
    13 years 8 months ago
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
    Download  home.dei.polimi.it
    Luca Penzo, Donatella Sciuto, Cristina Silvano
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    VLSID
    1995
    IEEE
    97views VLSI» more  VLSID 1995»
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
    13 years 8 months ago
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
    Download  www1.cs.columbia.edu
    In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
    Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
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    VLSID
    1995
    IEEE
    112views VLSI» more  VLSID 1995»
    An efficient automatic test generation system for path delay faults in combinational circuits
    13 years 8 months ago
    An efficient automatic test generation system for path delay faults in combinational circuits
    Download  eprints.iisc.ernet.in
    Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
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    VLSID
    1995
    IEEE
    104views VLSI» more  VLSID 1995»
    A VLSI architecture for the computation of NURBS patches
    13 years 8 months ago
    A VLSI architecture for the computation of NURBS patches
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    Meenakshisundaram Gopi, Swami Manohar
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    VLSID
    1995
    IEEE
    109views VLSI» more  VLSID 1995»
    Logic minimization based approach for compressing image data
    13 years 8 months ago
    Logic minimization based approach for compressing image data
    Download  eprints.iisc.ernet.in
    Jacob Augustine, Wen Feng, James Jacob
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    GLVLSI
    1995
    IEEE
    120views VLSI» more  GLVLSI 1995»
    Performance driven standard-cell placement using the genetic algorithm
    13 years 8 months ago
    Performance driven standard-cell placement using the genetic algorithm
    Download  www.kfupm.edu.sa
    Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muham...
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    GLVLSI
    1995
    IEEE
    118views VLSI» more  GLVLSI 1995»
    A new look at the conditions for the synthesis of speed-independent circuits
    13 years 8 months ago
    A new look at the conditions for the synthesis of speed-independent circuits
    Download  www.lsi.upc.es
    Enric Pastor, Jordi Cortadella, Oriol Roig
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