Sciweavers

Share
GLVLSI
1995
IEEE
104views VLSI» more  GLVLSI 1995»
8 years 7 months ago
Symbolic execution of data paths
Chuck Monahan, Forrest Brewer
GLVLSI
1995
IEEE
96views VLSI» more  GLVLSI 1995»
8 years 7 months ago
Thumbnail rectilinear Steiner trees
Joseph L. Ganley, James P. Cohoon
FCCM
1995
IEEE
135views VLSI» more  FCCM 1995»
8 years 7 months ago
Architectural descriptions for FPGA circuits
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
Satnam Singh
FCCM
1995
IEEE
97views VLSI» more  FCCM 1995»
8 years 7 months ago
Issues in wireless video coding using run-time-reconfigurable FPGAs
Brian Schoner, Chris Jones, John D. Villasenor
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
8 years 7 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
SPAA
2000
ACM
8 years 7 months ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
André DeHon
FCCM
1997
IEEE
106views VLSI» more  FCCM 1997»
8 years 7 months ago
Fault simulation on reconfigurable hardware
In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that ou...
Miron Abramovici, Premachandran R. Menon
ARVLSI
1995
IEEE
78views VLSI» more  ARVLSI 1995»
8 years 7 months ago
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Sch...
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
8 years 7 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
ARVLSI
1995
IEEE
117views VLSI» more  ARVLSI 1995»
8 years 7 months ago
Recursive layout generation
Louis Monier, Ramsey W. Haddad, Jeremy Dion
books