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ARVLSI
1995
IEEE
124views VLSI» more  ARVLSI 1995»
9 years 2 months ago
An evaluation of bipartitioning techniques
Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years. Numerous approaches have been developed and many diff...
Scott Hauck, Gaetano Borriello
ARVLSI
1995
IEEE
179views VLSI» more  ARVLSI 1995»
9 years 2 months ago
Algorithms for the optimal state assignment of asynchronous state machines
This paper presents a method for the optimal state assignment of asynchronous state machines. Unlike state assignment for synchronous state machines, state codes must be chosen ca...
Robert M. Fuhrer, Bill Lin, Steven M. Nowick
ARVLSI
1995
IEEE
132views VLSI» more  ARVLSI 1995»
9 years 2 months ago
Standard CMOS active pixel image sensors for multimedia applications
The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting...
Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid,...
ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
9 years 2 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
ARVLSI
1995
IEEE
155views VLSI» more  ARVLSI 1995»
9 years 2 months ago
Low-latency plesiochronous data retiming
A new method of retiming plesiochronous data is described. This method features latency of less than a cell-time and requires only minimal support circuitry. No flow control or ha...
Larry R. Dennison, William J. Dally, Thucydides Xa...
ARVLSI
1995
IEEE
151views VLSI» more  ARVLSI 1995»
9 years 2 months ago
Silicon VLSI processing architectures incorporating integrated optoelectronic devices
Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wi...
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
9 years 2 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
ARVLSI
1997
IEEE
138views VLSI» more  ARVLSI 1997»
9 years 2 months ago
Kestrel: Design of an 8-bit SIMD Parallel Processor
David M. Dahle, Jeffrey D. Hirschberg, Kevin Karpl...
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