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    VLSID
    2002
    IEEE
    120views VLSI» more  VLSID 2002»
    Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
    14 years 4 months ago
    Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
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    We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
    Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
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