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ACSD
2005
IEEE
67views Hardware» more  ACSD 2005»
13 years 5 months ago
Hazard Detection in a GALS Wrapper: A Case Study
An asynchronous wrapper of a fabricated GALS system is analyzed for hazards. For this purpose a Petri net based modelling approach of this GALS wrapper is presented. In our model ...
Christian Stahl, Wolfgang Reisig, Milos Krstic
ACSD
2005
IEEE
105views Hardware» more  ACSD 2005»
13 years 5 months ago
Dead-Path-Elimination in BPEL4WS
Franck van Breugel, Mariya Koshkina
ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
13 years 9 months ago
Extensible and Scalable Time Triggered Scheduling
The objective of this paper is to present how to design a system that can accommodate additional functionality with either no changes to the design or adding architectural modules...
Wei Zheng, Jike Chong, Claudio Pinello, Sri Kanaja...
ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
13 years 9 months ago
Improved Decomposition of STGs
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a...
Walter Vogler, Ben Kangsah
ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
13 years 9 months ago
Two-Phase Distributed Observation Problems
We introduce and study problems of distributed observation with bounded or unbounded memory. We are given a system modeled as a finite-word language L over some finite alphabet ...
Stavros Tripakis
ACSD
2005
IEEE
162views Hardware» more  ACSD 2005»
13 years 9 months ago
Complexity Results for Checking Distributed Implementability
We consider the distributed implementability problem as: Given a labeled transition system TS together with a distribution ∆ of its actions over a set of processes, does there ex...
Keijo Heljanko, Alin Stefanescu
ACSD
2005
IEEE
124views Hardware» more  ACSD 2005»
13 years 9 months ago
Safety-Liveness Semantics for UML 2.0 Sequence Diagrams
We provide an automata-theoretic solution to one of the main open questions about the UML standard, namely how to assign a formal semantics to a set of sequence diagrams without c...
Radu Grosu, Scott A. Smolka
ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
13 years 9 months ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
ACSD
2005
IEEE
103views Hardware» more  ACSD 2005»
13 years 9 months ago
An Algebra of Pareto Points
Marc Geilen, Twan Basten, Bart D. Theelen, Ralph O...