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TC
2008
11 years 9 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ANCS
2007
ACM
12 years 1 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
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