Sciweavers

IMC
2007
ACM
13 years 6 months ago
Usage-based dhcp lease time optimization
The Dynamic Host Configuration Protocol (DHCP) is used to dynamically allocate address space to hosts on a local area network. Despite its widespread usage, few studies exist on ...
Manas Khadilkar, Nick Feamster, Matt Sanders, Russ...
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 6 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
CSE
2009
IEEE
13 years 7 months ago
Socially Enhanced Network Address Translation
—The rapid evolution of the Internet has forced the use of Network Address Translation (NAT) to help slow the decline of publicly available IPv4 address space. While NAT provides...
Alexis Malozemoff, Muthucumaru Maheswaran
CLUSTER
2004
IEEE
13 years 8 months ago
An efficient end-host architecture for cluster communication
Cluster computing environments built from commodity hardware have provided a cost-effective solution for many scientific and high-performance applications. Likewise, middleware te...
Xin Qi, Gabriel Parmer, Richard West
SPDP
1993
IEEE
13 years 8 months ago
Fast Rehashing in PRAM Emulations
In PRAM emulations, universal hashing is a well-known method for distributing the address space among memory modules. However, if the memory access patterns of an application ofte...
J. Keller
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
13 years 8 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
ARCS
1997
Springer
13 years 8 months ago
A Novel Universal Sequencer Hardware
This paper introduces a powerful novel sequencer hardware for controlling computational machines and for structured DMA (direct memory access) applications. The paper introduces t...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
13 years 10 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
IPPS
2005
IEEE
13 years 10 months ago
Automatic Support for Irregular Computations in a High-Level Language
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
Jimmy Su, Katherine A. Yelick
CODES
2005
IEEE
13 years 10 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra