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    FPL
    2004
    Springer
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    Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
    13 years 8 months ago
    Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
    Download  www.eecs.northwestern.edu
    Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
    Joseph Zambreno, David Nguyen, Alok N. Choudhary
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