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APCCAS
2006
IEEE
292views Hardware» more  APCCAS 2006»
13 years 10 months ago
Another Look at the Sequential Multiplier over Normal Bases
—The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2m ), which can perform multiplication in m clock cycles for the normal basis. In this ar...
Zih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Y...
APCCAS
2006
IEEE
249views Hardware» more  APCCAS 2006»
13 years 10 months ago
Uncertainty Management for Estimation in Dynamical Systems
— A novel black-box model for time series of prices analysis is proposed. It is constructed using the technique of “shaping filter”. The model identification is then propos...
H. Baili
APCCAS
2006
IEEE
307views Hardware» more  APCCAS 2006»
13 years 10 months ago
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
APCCAS
2006
IEEE
229views Hardware» more  APCCAS 2006»
13 years 10 months ago
Low Power Combinational Multipliers using Data-driven Signal Gating
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
Nima Honarmand, Ali Afzali-Kusha
APCCAS
2006
IEEE
271views Hardware» more  APCCAS 2006»
13 years 10 months ago
Leakage Optimized DECAP Design for FPGAs
— On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associa...
Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, ...
APCCAS
2006
IEEE
296views Hardware» more  APCCAS 2006»
13 years 10 months ago
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
Yasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekin...
APCCAS
2006
IEEE
251views Hardware» more  APCCAS 2006»
13 years 10 months ago
Implementation of a H.264 decoder with Template-based Communication Refinement
We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with ...
Sang-yong Yoon, Sanggyu Park, Soolk Chae
APCCAS
2006
IEEE
268views Hardware» more  APCCAS 2006»
13 years 10 months ago
A One-Dimensional Technique for Embedding Data in A JPEG Color Image
—A method of embedding data in a JPEG color image for applications such as authentication of an employee carrying a picture identification card is described. Embedding of data, s...
Kaliappan Gopalan
APCCAS
2006
IEEE
233views Hardware» more  APCCAS 2006»
13 years 10 months ago
Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters
— In recent years, several approaches have been proposed aiming the optimal joint design of finite impulse response (FIR) multiple-input multiple-output (MIMO) transmitter and r...
Guilherme Pinto, Paulo S. R. Diniz, Are Hjø...
APCCAS
2006
IEEE
253views Hardware» more  APCCAS 2006»
13 years 10 months ago
Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image Coding
— The DCT-based JPEG standard is certainly one of the most successful applications of transform coding methods for still digital images. A commonly recognized disadvantage of the...
Wu-Sheng Lu, A.-M. Sevcenco