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APCSAC
2003
IEEE
9 years 7 months ago
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran
APCSAC
2003
IEEE
9 years 7 months ago
On Implementing High Level Concurrency in Java
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...
G. Stewart Von Itzstein, Mark Jasiunas
APCSAC
2003
IEEE
9 years 9 months ago
Towards an Asynchronous MIPS Processor
Qianyi Zhang, Georgios K. Theodoropoulos
APCSAC
2003
IEEE
9 years 9 months ago
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor
The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...
Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot H...
APCSAC
2003
IEEE
9 years 9 months ago
Reducing Access Count to Register-Files through Operand Reuse
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
APCSAC
2003
IEEE
9 years 9 months ago
A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks
Static nodes, e.g. houses, educational institutions etc, can comprise ad-hoc networks using off-the-self wireless technologies with a view to bypass expensive telecommunication so...
Muhammad Mahmudul Islam, Ronald Pose, Carlo Kopp
APCSAC
2003
IEEE
9 years 9 months ago
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
Philip Machanick, Zunaid Patel
APCSAC
2003
IEEE
9 years 9 months ago
Latency Improvement in Virtual Multicasting
Virtual multicasting (VMC) combines some of the benefits of caching (transparency, dynamic adaptation to workload) and multicasting (reducing duplicated traffic). Virtual multicas...
Philip Machanick, Brynn Andrew
APCSAC
2003
IEEE
9 years 9 months ago
User-Level Management of Kernel Memory
Abstract. Kernel memory is a resource that must be managed carefully in order to ensure the efficiency and safety of the system. The use of an inappropriate management policy can w...
Andreas Haeberlen, Kevin Elphinstone
APCSAC
2003
IEEE
9 years 9 months ago
Mapping Applications to a Coarse Grain Reconfigurable System
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Mi...
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