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JSS
2007
75views more  JSS 2007»
9 years 3 months ago
A rationale-based architecture model for design traceability and reasoning
Large systems often have a long life-span and comprise many intricately related elements. The verification and maintenance of these systems require a good understanding of their ...
Antony Tang, Yan Jin, Jun Han
WICSA
2004
9 years 5 months ago
Establishing a Software Architecting Environment
We present the work of establishing an integrated environment that facilitates architecture design, reconstruction, and maintenance in the entire life cycle of a software product ...
Claudio Riva, Petri Selonen, Tarja Systä, Ant...
ISORC
1998
IEEE
9 years 8 months ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz
ICSE
1999
IEEE-ACM
9 years 8 months ago
Haemo Dialysis Software Architecture Design Experiences
In this paper we present the experiences and architecture from a research project conducted in cooperation with two industry partners. The goal of the project was to reengineer an...
PerOlof Bengtsson, Jan Bosch
COMPSAC
1999
IEEE
9 years 8 months ago
Dynamic Software Architecture Slicing
As the complexity of software systems increases, so need for a good mechanism of abstraction. architecture design is an abstraction, hiding an immense amount of details about the ...
Taeho Kim, Yeong-Tae Song, Lawrence Chung, Dung T....
CAMP
2000
IEEE
9 years 8 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
9 years 9 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills
ICECCS
2005
IEEE
108views Hardware» more  ICECCS 2005»
9 years 9 months ago
Evolving Messaging Systems for Secure Role Based Messaging
This paper articulates a system design for the secure role based messaging model built based on existing messaging systems, public key infrastructures, and a privilege management ...
Gansen Zhao, David W. Chadwick
ECBS
2005
IEEE
162views Hardware» more  ECBS 2005»
9 years 9 months ago
Architecture Rationalization: A Methodology for Architecture Verifiability, Traceability and Completeness
Architecture modeling is practiced extensively in the software industry but there is little attention paid to the traceability, verifiability and completeness of architecture desi...
Antony Tang, Jun Han
IISWC
2008
IEEE
9 years 10 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
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