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ARITH
2003
IEEE
13 years 9 months ago
The Case for a Redundant Format in Floating Point Arithmetic
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic opera...
Hossam A. H. Fahmy, Michael J. Flynn
ARITH
2003
IEEE
13 years 9 months ago
Decimal Floating-Point: Algorism for Computers
Decimal arithmetic is the norm in human calculations, and human-centric applications must use a decimal floating-point arithmetic to achieve the same results. Initial benchmarks i...
Michael F. Cowlishaw
ARITH
2003
IEEE
13 years 9 months ago
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we descri...
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliad...
ARITH
2003
IEEE
13 years 9 months ago
Scaling an RNS Number Using the Core Function
This paper introduces a method for extracting the core of a Residue Number System (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS ...
Neil Burgess
ARITH
2003
IEEE
13 years 9 months ago
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
Soonhak Kwon
ARITH
2003
IEEE
13 years 9 months ago
Some Optimizations of Hardware Multiplication by Constant Matrices
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant m...
Nicolas Boullis, Arnaud Tisserand
ARITH
2003
IEEE
13 years 9 months ago
Revisiting SRT Quotient Digit Selection
The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a r...
Peter Kornerup
ARITH
2003
IEEE
13 years 9 months ago
Saturating Counters: Application and Design Alternatives
We define a new class of parallel counters, Saturating Counters, which provide the exact count of the inputs that are 1 only if this count is below a given threshold. Such counte...
Israel Koren, Yaron Koren, Bejoy G. Oomman
ARITH
2003
IEEE
13 years 9 months ago
A VLSI Algorithm for Modular Multiplication/Division
We propose an algorithm for modular multiplication/division suitable for VLSI implementation. The algorithm is based on Montgomery’s method for modular multiplication and on the...
Marcelo E. Kaihara, Naofumi Takagi