ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
The draft revision of the IEEE Standard for FloatingPoint Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP s...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
In the present paper, we investigate the approximation of a function by a polynomial with floating-point coefficients; we are looking for the best approximation in the L2 sense....
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...