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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 7 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
ARVLSI
1997
IEEE
138views VLSI» more  ARVLSI 1997»
13 years 7 months ago
Kestrel: Design of an 8-bit SIMD Parallel Processor
David M. Dahle, Jeffrey D. Hirschberg, Kevin Karpl...
ARVLSI
1997
IEEE
103views VLSI» more  ARVLSI 1997»
13 years 7 months ago
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
George Kornaros, Christoforos E. Kozyrakis, Panagi...
ARVLSI
1997
IEEE
96views VLSI» more  ARVLSI 1997»
13 years 7 months ago
Circuits and Microarchitecture for Gigahertz VLSI Designs
IBM founded the Austin Research Laboratory to investigate high-performance microprocessorbased systems. Initial e orts have focused on design for high frequency. This resulted in ...
Kevin J. Nowka, H. Peter Hofstee
ARVLSI
1997
IEEE
89views VLSI» more  ARVLSI 1997»
13 years 7 months ago
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity
V. Chandramouli, Karem A. Sakallah, Ayman I. Kayss...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
13 years 7 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
13 years 7 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton