Sciweavers

Share
ASAP
1997
IEEE
155views Hardware» more  ASAP 1997»
9 years 7 months ago
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
ASAP
1997
IEEE
107views Hardware» more  ASAP 1997»
9 years 7 months ago
Tiling with limited resources
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to ...
Pierre-Yves Calland, Jack Dongarra, Yves Robert
ASAP
1997
IEEE
92views Hardware» more  ASAP 1997»
9 years 7 months ago
Optimized software synthesis for synchronous dataflow
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward...
ASAP
1997
IEEE
139views Hardware» more  ASAP 1997»
9 years 7 months ago
Buffer size optimization for full-search block matching algorithms
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus i...
Yuan-Hau Yeh, Chen-Yi Lee
ASAP
1997
IEEE
112views Hardware» more  ASAP 1997»
9 years 7 months ago
Low latency word serial CORDIC
Julio Villalba, Tomás Lang
ASAP
1997
IEEE
93views Hardware» more  ASAP 1997»
9 years 7 months ago
A Novel Sequencer Hardware for Application Specific Computing
This paper introduces a powerful novel sequencer for controlling computational machines and for structured DMA (direct memory access) applications. It is mainly focused on applica...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ASAP
1997
IEEE
100views Hardware» more  ASAP 1997»
9 years 7 months ago
Processor Elements for the Standard Cell Implementation of Residue Number Systems
In this article processor elements for the effective implementation of standard cell circuits based on Residue Number Systems (RNS) are presented. Two new processors are proposed ...
Ansgar Drolshagen, H. Henkelmann, Walter Anheier
ASAP
1997
IEEE
106views Hardware» more  ASAP 1997»
9 years 7 months ago
Libraries of schedule-free operators in Alpha
This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial ...
Florent de Dinechin
books