Sciweavers

ASAP
2007
IEEE
97views Hardware» more  ASAP 2007»
13 years 6 months ago
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, ...
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 8 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
ASAP
2007
IEEE
130views Hardware» more  ASAP 2007»
13 years 8 months ago
A Self-Reconfigurable Implementation of the JPEG Encoder
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ASAP
2007
IEEE
203views Hardware» more  ASAP 2007»
13 years 8 months ago
Reconfigurable Universal Adder
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
ASAP
2007
IEEE
157views Hardware» more  ASAP 2007»
13 years 8 months ago
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations
Monte-Carlo simulations are used in many applications, such as option pricing and portfolio evaluation. Due to their high computational load and intrinsic parallelism, they are id...
David B. Thomas, Jacob A. Bower, Wayne Luk
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
13 years 8 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
ASAP
2007
IEEE
91views Hardware» more  ASAP 2007»
13 years 10 months ago
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs
Gianluca Palermo, Giovanni Mariani, Cristina Silva...
ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
13 years 10 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
13 years 10 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 10 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong