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ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
13 years 7 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
13 years 9 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit