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ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
9 years 11 months ago
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Teru...
ASPDAC
1999
ACM
101views Hardware» more  ASPDAC 1999»
9 years 11 months ago
Optimal Evaluation Clocking of Self-Resetting Domino Pipelines
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
Kenneth Y. Yun, Ayoob E. Dooply
ASPDAC
1999
ACM
143views Hardware» more  ASPDAC 1999»
9 years 11 months ago
Crosstalk Reduction by Transistor Sizing
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
Tong Xiao, Malgorzata Marek-Sadowska
ASPDAC
1999
ACM
137views Hardware» more  ASPDAC 1999»
9 years 11 months ago
A Performance-Driven I/O Pin Routing Algorithm
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arun...
ASPDAC
1999
ACM
87views Hardware» more  ASPDAC 1999»
9 years 11 months ago
VCO Jitter Simulation and Its Comparison With Measurement
Masayuki Takahashi, Kimihiro Ogawa, Kenneth S. Kun...
ASPDAC
1999
ACM
98views Hardware» more  ASPDAC 1999»
9 years 11 months ago
A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler
− In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from...
Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihi...
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
9 years 11 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
ASPDAC
1999
ACM
168views Hardware» more  ASPDAC 1999»
9 years 11 months ago
An Integrated Battery-Hardware Model for Portable Electronics
- We describe an integrated model of the hardware and the battery sub-systems in batterypowered VLSI systems. We demonstrate that, under this model and for a fixed operating voltag...
Massoud Pedram, Chi-Ying Tsui, Qing Wu
ASPDAC
1999
ACM
117views Hardware» more  ASPDAC 1999»
9 years 11 months ago
Analysing Forced Oscillators with Multiple Time Scales
We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency mo...
Onuttom Narayan, Jaijeet S. Roychowdhury
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