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ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
13 years 8 months ago
Genetic algorithm accelerator GAA-II
We have developed a new GA hardware called GAA-I (Genetic Algorithm Accelerator-I), in which the crossover operator to be applied to each individual was dynamically selected during...
Shin'ichi Wakabayashi, Tetsushi Koide, Nayoshi Tos...
ASPDAC
2000
ACM
112views Hardware» more  ASPDAC 2000»
13 years 8 months ago
An introduction to SLDL and Rosetta
Steven E. Schultz
ASPDAC
2000
ACM
131views Hardware» more  ASPDAC 2000»
13 years 8 months ago
Reconfigurable synchronized dataflow processor
- This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow ...
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka...
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
13 years 8 months ago
Multi-clock path analysis using propositional satisfiability
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, ...
ASPDAC
2000
ACM
133views Hardware» more  ASPDAC 2000»
13 years 8 months ago
A VLSI implementation of the blowfish encryption/decryption algorithm
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-reschedul...
Michael C.-J. Lin, Youn-Long Lin
ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
13 years 8 months ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...
ASPDAC
2000
ACM
157views Hardware» more  ASPDAC 2000»
13 years 8 months ago
An application specific Java processor with reconfigurabilities
The paper presents an application specific Java processor including reconfigurabilities, which is a DLX like pipeline processor with 5 stages and executes Java byte codes directly....
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Ta...
ASPDAC
2000
ACM
96views Hardware» more  ASPDAC 2000»
13 years 8 months ago
A programmable built-in self-test core for embedded memories
Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a progr...
Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu