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ASPDAC
2001
ACM
103views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Efficient minimum spanning tree construction without Delaunay triangulation
Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs o...
Hai Zhou, Narendra V. Shenoy, William Nicholls
ASPDAC
2001
ACM
91views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Cell selection from technology libraries for minimizing power
Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
13 years 8 months ago
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors...
Zhaozhi Yang, Zeyi Wang, Shuzhou Fang
ASPDAC
2001
ACM
81views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Low-power high-level synthesis using latches
Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung
ASPDAC
2001
ACM
101views Hardware» more  ASPDAC 2001»
13 years 8 months ago
A statistical static timing analysis considering correlations between delays
Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Processor-programmable memory BIST for bus-connected embedded memories
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
Ching-Hong Tsai, Cheng-Wen Wu
ASPDAC
2001
ACM
68views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Reducing bus delay in submicron technology using coding
ct,. In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire mqd...
Paul-Peter Sotiriadis, Anantha Chandrakasan
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
13 years 8 months ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart