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    ASPDAC
    2005
    ACM
    131views Hardware» more  ASPDAC 2005»
    Analysis of buffered hybrid structured clock networks
    13 years 6 months ago
    Analysis of buffered hybrid structured clock networks
    Download  www.ee.ucr.edu
    - This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
    Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
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    ASPDAC
    2005
    ACM
    90views Hardware» more  ASPDAC 2005»
    An integrated performance and power model for superscalar processor designs
    13 years 6 months ago
    An integrated performance and power model for superscalar processor designs
    Download  www.comp.nus.edu.sg
    — On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
    Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
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    ASPDAC
    2005
    ACM
    95views Hardware» more  ASPDAC 2005»
    Buffering global interconnects in structured ASIC design
    13 years 6 months ago
    Buffering global interconnects in structured ASIC design
    Download  www.ece.umn.edu
    Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wire...
    Tianpei Zhang, Sachin S. Sapatnekar
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    ASPDAC
    2005
    ACM
    116views Hardware» more  ASPDAC 2005»
    On combining iteration space tiling with data space tiling for scratch-pad memory systems
    13 years 6 months ago
    On combining iteration space tiling with data space tiling for scratch-pad memory systems
    Download  www.cecs.uci.edu
    Abstract— Most previous studies on tiling concentrate on iteration space only for cache-based memory systems. However, more and more real-time embedded systems are adopting Scrat...
    Chunhui Zhang, Fadi J. Kurdahi
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    ASPDAC
    2005
    ACM
    122views Hardware» more  ASPDAC 2005»
    Block based statistical timing analysis with extended canonical timing model
    13 years 6 months ago
    Block based statistical timing analysis with extended canonical timing model
    Download  vlsi.ece.wisc.edu
    Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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    ASPDAC
    2005
    ACM
    111views Hardware» more  ASPDAC 2005»
    Wave-pipelined on-chip global interconnect
    13 years 6 months ago
    Wave-pipelined on-chip global interconnect
    Download  cc.ee.ntu.edu.tw
    — A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
    Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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    ASPDAC
    2005
    ACM
    101views Hardware» more  ASPDAC 2005»
    A wideband hierarchical circuit reduction for massively coupled interconnects
    13 years 6 months ago
    A wideband hierarchical circuit reduction for massively coupled interconnects
    Download  www.ee.ucr.edu
    — We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
    Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
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    ASPDAC
    2005
    ACM
    104views Hardware» more  ASPDAC 2005»
    Low-power techniques for network security processors
    13 years 6 months ago
    Low-power techniques for network security processors
    Download  www.cs.nctu.edu.tw
    Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
    Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu...
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    ASPDAC
    2005
    ACM
    132views Hardware» more  ASPDAC 2005»
    Automatic synthesis and scheduling of multirate DSP algorithms
    13 years 6 months ago
    Automatic synthesis and scheduling of multirate DSP algorithms
    Download  www.see.ed.ac.uk
    - To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
    Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
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    ASPDAC
    2005
    ACM
    99views Hardware» more  ASPDAC 2005»
    Implication of assertion graphs in GSTE
    13 years 6 months ago
    Implication of assertion graphs in GSTE
    Download  web.cecs.pdx.edu
    - We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
    Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...
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