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ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
9 years 3 months ago
An integrated performance and power model for superscalar processor designs
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
ASPDAC
2005
ACM
95views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Buffering global interconnects in structured ASIC design
Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wire...
Tianpei Zhang, Sachin S. Sapatnekar
ASPDAC
2005
ACM
116views Hardware» more  ASPDAC 2005»
9 years 3 months ago
On combining iteration space tiling with data space tiling for scratch-pad memory systems
Abstract— Most previous studies on tiling concentrate on iteration space only for cache-based memory systems. However, more and more real-time embedded systems are adopting Scrat...
Chunhui Zhang, Fadi J. Kurdahi
ASPDAC
2005
ACM
122views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Block based statistical timing analysis with extended canonical timing model
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
9 years 3 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Low-power techniques for network security processors
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu...
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
9 years 3 months ago
Implication of assertion graphs in GSTE
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...
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