ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— Motivated by VLSI/ULSI routing applications, we present a heuristic for rectilinear Steiner minimal tree (RSMT) construction. We transform a rectilinear minimum spanning tree (...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— This paper propose a systematic method to select power/ground wires that should be considered in interconnect RL extraction. The return current distribution affects loop charac...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Abstract— This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noi...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...