ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Due to increasing clock speeds and shrinking technologies, distributing a single global clock signal throughout a chip is becoming a difficult and challenging proposition. In this...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flo...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
It has been shown that Binary Decision Diagram (BDD) based logic synthesis enjoys faster runtime than the classic logic synthesis systems based on Sum of Product (SOP) form. Howev...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed sdomain h...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Ever scaling process technology makes embedded systems more vulnerable to soft errors than in the past. One of the generic methods used to fight soft errors is based on duplicati...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
- This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumpti...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...