Sciweavers

ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Placement with symmetry constraints for analog layout design using TCG-S
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hu...
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
13 years 6 months ago
System-level design space exploration for security processor prototyping in analytical approaches
— The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration o...
Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Design and design automation of rectification logic for engineering change
In a later stage of a VLSI design, it is quite often to modify a design implementation to accommodate the new specification, design errors, or to meet design constraints. In addit...
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang...
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Feasibility analysis of messages for on-chip networks using wormhole routing
—The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing propert...
Zhonghai Lu, Axel Jantsch, Ingo Sander
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 6 months ago
On-chip accumulated jitter measurement for phase-locked loops
Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Making fast buffer insertion even faster via approximation techniques
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang...
ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Oscillation ring based interconnect test scheme for SOC
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Floorplan management: incremental placement for gate sizing and buffer insertion
Incremental physical design is an important methodology towards achieving design closure for high-performance large-scale circuits. Placement tools must accommodate incremental ch...
Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden