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ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Hardware debugging method based on signal transitions and transactions
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
Nobuyuki Ohba, Kohji Takano
ASPDAC
2006
ACM
123views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
- We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent f...
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan...
ASPDAC
2006
ACM
125views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Efficient identification of multi-cycle false path
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
Kai Yang, Kwang-Ting Cheng
ASPDAC
2006
ACM
173views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...
ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ASPDAC
2006
ACM
176views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
Abstract-- This paper presents a fundamental result on buffer sizing. Given an interconnection wire with n buffers evenly spaced along the wire, we would like to size all buffers s...
Sebastian Vogel, Martin D. F. Wong
ASPDAC
2006
ACM
128views Hardware» more  ASPDAC 2006»
8 years 11 months ago
FastPlace 2.0: an efficient analytical placer for mixed-mode designs
Abstract-- In this paper, we present FastPlace 2.0
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
ASPDAC
2006
ACM
121views Hardware» more  ASPDAC 2006»
8 years 11 months ago
Efficient early stage resonance estimation techniques for C4 package
- In this paper, we study the relationship between C4 package resonance effects and logical switching timing correlations, which has not been thoroughly investigated in the past. W...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
ASPDAC
2006
ACM
145views Hardware» more  ASPDAC 2006»
8 years 11 months ago
FSM-based transaction-level functional coverage for interface compliance verification
Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Ya...
ASPDAC
2006
ACM
128views Hardware» more  ASPDAC 2006»
8 years 11 months ago
A new test and characterization scheme for 10+ GHz low jitter wide band PLL
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
Kazuhiko Miki, David Boerstler, Eskinder Hailu, Ji...
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