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ASPDAC
2006
ACM
93views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Electrothermal analysis and optimization techniques for nanoscale integrated circuits
Abstract— With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of ele...
Yong Zhan, Brent Goplen, Sachin S. Sapatnekar
ASPDAC
2006
ACM
146views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A fixed-die floorplanning algorithm using an analytical approach
— Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the t...
Yong Zhan, Yan Feng, Sachin S. Sapatnekar
ASPDAC
2006
ACM
101views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Worst case execution time analysis for synthesized hardware
- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on s...
Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Adaptive admittance-based conductor meshing for interconnect analysis
Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakri...
ASPDAC
2006
ACM
106views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method
— A complete multiple reciprocity method (CMRM), usually for the eigenvalue analysis of Helmholtz equation, is introduced to the BEM for frequency-dependent inductance extraction...
Changhao Yan, Wenjian Yu, Zeyi Wang
ASPDAC
2006
ACM
82views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A transduction-based framework to synthesize RSFQ circuits
Shigeru Yamashita, Katsunori Tanaka, Hideyuki Taka...
ASPDAC
2006
ACM
91views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Statistical corner conditions of interconnect delay (corner LPE specifications)
- Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. I...
Kenta Yamada, Noriaki Oda
ASPDAC
2006
ACM
113views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Transition-based coverage estimation for symbolic model checking
— Lack of complete formal specification is one of the major obstacles for the deployment of model checking. Coverage estimation addresses this issue by revealing the unverified...
Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Take...
ASPDAC
2006
ACM
134views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Constraint driven I/O planning and placement for chip-package co-design
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He