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ASPDAC
2006
ACM
114views Hardware» more  ASPDAC 2006»
13 years 9 months ago
High level equivalence symmetric input identification
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
Ming-Hong Su, Chun-Yao Wang
ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
13 years 9 months ago
A memory grouping method for sharing memory BIST logic
- With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST lo...
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
ASPDAC
2006
ACM
94views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Mapping and configuration methods for multi-use-case networks on chips
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
13 years 9 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
ASPDAC
2006
ACM
114views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Yield-preferred via insertion based on novel geotopological technology
Fangyi Luo, Yongbo Jia, Wayne Wei-Ming Dai
ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Design space exploration for minimizing multi-project wafer production cost
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-...
ASPDAC
2006
ACM
288views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Algorithms and DSP implementation of H.264/AVC
Abstract - This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, partic...
Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-...
ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
13 years 9 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
13 years 9 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi