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ASPDAC
2007
ACM
106views Hardware» more  ASPDAC 2007»
10 years 1 months ago
Bisection Based Placement for the X Architecture
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...
Satoshi Ono, Sameer Tilak, Patrick H. Madden
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
10 years 1 months ago
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation
In the paper, we develop a systematic methodology for modeling sampled interconnect frequency response data based on spline interpolation. Through piecewise polynomial interpolatio...
Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud
ASPDAC
2007
ACM
85views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den D...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
- A Cyclic-CPRS (Column Parity Row Selection) technique is presented to diagnose built-in self tested (BISTed) circuits, even in the presence of many unknowns and transient errors....
Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Ch...
ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
10 years 3 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
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