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ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
13 years 8 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASPDAC
2007
ACM
92views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
13 years 8 months ago
FastRoute 2.0: A High-quality and Efficient Global Router
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interco...
Min Pan, Chris C. N. Chu
ASPDAC
2007
ACM
114views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Automating Logic Rectification by Approximate SPFDs
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Vener...
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems
Abstract-- The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to mi...
Soumyajit Dey, Monu Kedia, Anupam Basu
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Low-Power High-Speed 180-nm CMOS Clock Drivers
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...
ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine ...
Axel Siebenborn, Alexander Viehl, Oliver Bringmann...
ASPDAC
2007
ACM
64views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlo...
ASPDAC
2007
ACM
94views Hardware» more  ASPDAC 2007»
13 years 8 months ago
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates
-1 The couplings via realistic lossy substrates can be modeled as frequency-dependent coupling parameters. The fast extraction at multiple frequencies can be accomplished in two se...
Xiren Wang, Wenjian Yu, Zeyi Wang