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ASPDAC
2007
ACM
152views Hardware» more  ASPDAC 2007»
10 years 5 months ago
A Graph Reduction Approach to Symbolic Circuit Analysis
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Trace Compaction using SAT-based Reachability Analysis
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
Sean Safarpour, Andreas G. Veneris, Hratch Mangass...
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
10 years 5 months ago
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design
Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, ...
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Retiming for Synchronous Data Flow Graphs
Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou,...
ASPDAC
2007
ACM
74views Hardware» more  ASPDAC 2007»
10 years 5 months ago
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks
How to estimate the shortest routing length when certain blocks are considered as routing obstacles is becoming an essential problem for block placement because HPWL is no longer v...
Tan Yan, Shuting Li, Yasuhiro Takashima, H. Murata
ASPDAC
2007
ACM
102views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
Chuan Lin, Hai Zhou
ASPDAC
2007
ACM
90views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical des...
Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-...
ASPDAC
2007
ACM
90views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Protocol Transducer Synthesis using Divide and Conquer approach
One of the efficient design methodologies for large scale System on a Chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and intercon...
Shigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satosh...
ASPDAC
2007
ACM
77views Hardware» more  ASPDAC 2007»
10 years 5 months ago
Hippocrates: First-Do-No-Harm Detailed Placement
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-J...
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