ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
How to estimate the shortest routing length when certain blocks are considered as routing obstacles is becoming an essential problem for block placement because HPWL is no longer v...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical des...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
One of the efficient design methodologies for large scale System on a Chip (SoC) is IP-based design. In this methodology, a system is considered as a set of components and intercon...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...