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ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
9 years 10 months ago
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Webe...
ASPDAC
2008
ACM
102views Hardware» more  ASPDAC 2008»
9 years 10 months ago
Duo-binary circular turbo decoder based on border metric encoding for WiMAX
- This paper presents a duo-binary circular turbo decoder based on border metric encoding. With the proposed method, the memory size for branch memory is reduced by half and the du...
Ji-Hoon Kim, In-Cheol Park
ASPDAC
2008
ACM
100views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages
Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in...
Yoichi Tomioka, Atsushi Takahashi
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Analytical model for the impact of multiple input switching noise on timing
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He
ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
9 years 11 months ago
Efficient symbolic multi-objective design space exploration
-- Nowadays many design space exploration tools are based on Multi
Martin Lukasiewycz, Michael Glaß, Christian ...
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