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ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
9 years 11 days ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
ASPDAC
2009
ACM
153views Hardware» more  ASPDAC 2009»
9 years 11 days ago
A 3D prototyping chip based on a wafer-level stacking technology
We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stac...
Nobuaki Miyakawa
ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
9 years 3 months ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...
ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
9 years 3 months ago
A criticality-driven microarchitectural three dimensional (3D) floorplanner
- As technology scales, interconnect delays begin to dominate the performance of modern microprocessors. The ability to reduce the length of global wires has become an important de...
Srinath Sridharan, Michael DeBole, Guangyu Sun, Yu...
ASPDAC
2009
ACM
109views Hardware» more  ASPDAC 2009»
9 years 3 months ago
Soft lists: a native index structure for NOR-flash-based embedded devices
Efficient data indexing is significant to embedded devices, because both CPU cycles and energy are very precious resources. Soft lists, a new index structure for embedded devices w...
Li-Pin Chang, Chen-Hui Hsu
ASPDAC
2009
ACM
113views Hardware» more  ASPDAC 2009»
9 years 5 months ago
Post-routing redundant via insertion with wire spreading capability
—Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transforme...
Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee
ASPDAC
2009
ACM
160views Hardware» more  ASPDAC 2009»
9 years 5 months ago
CAD challenges for 3D ICs
David S. Kung, Ruchir Puri
ASPDAC
2009
ACM
112views Hardware» more  ASPDAC 2009»
9 years 6 months ago
Compiler-managed register file protection for energy-efficient soft error reduction
Abstract-- For embedded systems where neither energy nor reliability can be easily sacrificed, we present an energy efficient soft error protection scheme for register files (RF). ...
Jongeun Lee, Aviral Shrivastava
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
9 years 6 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
ASPDAC
2009
ACM
190views Hardware» more  ASPDAC 2009»
9 years 6 months ago
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
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