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ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
13 years 11 months ago
A multilevel analytical placement for 3D ICs
Jason Cong, Guojie Luo
ASPDAC
2009
ACM
150views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Using a dataflow abstracted virtual prototype for HdS-design
Dataflow abstracted Virtual Prototype for HdS-Design Wolfgang Ecker Stefan Heinen Michael Velten Infineon Technologies AG Germany ASPDAC 2009 Special Session Hardware-dependent Sof...
Wolfgang Ecker, Stefan Heinen, Michael Velten
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
13 years 11 months ago
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
- We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of
Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yan...
ASPDAC
2009
ACM
102views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips’ working freq...
Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
13 years 11 months ago
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction
Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo