ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
Wediscuss response timeproperties of linear arrays and tree-like arrays of cells with various handshake communication behaviours. The response times of a networkare the delays bet...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the fo...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents an in-depth case study in highperformance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rai...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
